Hi,
From hardware perspective, what's the purpose of WACK and RACK and how does it affect the ACE protocol ?
I can see that the specification says the master issues these two signals to indicate to the interconnect that Write and Read transactions completed
successfully at the master.
What happens on the ACE interface/protocol if NO WACK and RACK occur ?
Please provide some detailed explanations of proper operation of WACK and RACK and improper operation (what if no WACK / RACK occur).
Also, do these two signals (WACK,RACK) occur when WVALID , RVALID , respectively, are still high ?
Are WACK and RACK totally independent of WVALID, RVALID ?
The ACE spec doesn't show any waveform relationship for WVALID, RVALID with respect to WACK and RACK.
Thanks,
David
Hi Christopher! Thanks for the clear explanation. Through your explanation, I fully understand the purpose of the RACK handshake. But I really don't understand the purpose of the WACK handshake. I've imagined various scenarios, including CopyBack/Snoop race, WriteUnique/Snoop race, but none of them necessitates the WACK handshake. Would you give an example where WACK is a must?
Thanks!
Without WACK you can end up with more subtle ordering issues where different components see transactions occurring in a different order, which could make a component harder to design. For example, say we have M0 issuing a WriteUnique and M1 issuing a ReadUnique.
- Both managers issue their request at approximately the same time.
- M0's WriteUnique is ordered first by the interconnect, completes all its actions and the interconnect returns a B response back to M0.
- Without the WACK, the interconnect could immediately issue the snoop for the ReadUnique. This could overtake the B response back to M0.
- To M0, it now appears that the ReadUnique was ordered ahead of the WriteUnique. However, to the rest of the system the WriteUnique was ordered first.
With the WACK, the ReadUnique would not be able to make progress until M0 had received the B response.