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Configuration options for cxapbic for 32 masters and 2 slaves

Sid

!

Hi everyone,

I am new to Amba Designer tool and ARM IP.

Barely scratching surface.

Recently I have been trying to create a config.xml file for cxapbic (Apb bus related interconnect) for 32 masters and 2 slaves.

I realized that the 1st 4KB are reserved for ROM table. And 1st master address can start from 4Kb+1 location at most.

From what I know is that, the base address of the master needs to be on the boundary of magnitude of size of the master.

Basically 4KB master can start at 4KB boundary, 1MB master should always start at 1MB boundary.

So, is it that if I have 1 master whose range is 4MB, 32 masters each of 4KB, then I should start the first master form 4MB boundary which is then followed by 32 masters each of 4KB?

This will unnecessarily waste address range form 4KB to first 4MB boundary.

Even if I put 32 master each of 4KB just after the ROM table then the Master with 4MB will still be put on next 4MB boundary, still making hole between 32nd Master and next master who is of size 4MB.

Or I can still start immediately after ROM table ends at 4KB boundary thus making the master address range as 4KB+1 to 4KB+1+4MB, then followed 32masters of 4KB each?

And in this case I won't have holes in the address range of APBIC?

Any inputs are much appreciated.

Thanks.

Parents
  • +1

    Hi sidkadam,

    I don't have much experience in APB Interconnect with ROM table, I'll just give an opinion based on fundamental knowledge.

    Even if I put 32 master each of 4KB just after the ROM table then the Master with 4MB will still be put on next 4MB boundary, still making hole between 32nd Master and next master who is of size 4MB.

    I think this is the better option, regardless if the holes are usable or not.

    With this option you

    • only span the first 8 MB boundary.
    • only have 3964 KB (4 MB - 128 KB - 4 KB) hole in the first 4 MB.
    • leave the second 8 MB space vacant (entire 8 MB available).

    In the other option you

    • will transcend the first 8 MB boundary.
    • have wider, 4092 KB (4 MB - 4 KB) hole in the first 4 MB.
    • used 128 KB space above the first 8 MB and the largest vacant boundary in the second 8 MB space is only 4 MB (at the fourth 4 MB boundary).
    • increase the possibility of creating additional holes in the second 8 MB space. For example, you claim the vacant 4 MB in the second 8 MB space, your additional hole is 3968 KB (4 MB - 128 KB) in the third 4 MB space.

    Regards,

    Goodwin

Reply
  • +1

    Hi sidkadam,

    I don't have much experience in APB Interconnect with ROM table, I'll just give an opinion based on fundamental knowledge.

    Even if I put 32 master each of 4KB just after the ROM table then the Master with 4MB will still be put on next 4MB boundary, still making hole between 32nd Master and next master who is of size 4MB.

    I think this is the better option, regardless if the holes are usable or not.

    With this option you

    • only span the first 8 MB boundary.
    • only have 3964 KB (4 MB - 128 KB - 4 KB) hole in the first 4 MB.
    • leave the second 8 MB space vacant (entire 8 MB available).

    In the other option you

    • will transcend the first 8 MB boundary.
    • have wider, 4092 KB (4 MB - 4 KB) hole in the first 4 MB.
    • used 128 KB space above the first 8 MB and the largest vacant boundary in the second 8 MB space is only 4 MB (at the fourth 4 MB boundary).
    • increase the possibility of creating additional holes in the second 8 MB space. For example, you claim the vacant 4 MB in the second 8 MB space, your additional hole is 3968 KB (4 MB - 128 KB) in the third 4 MB space.

    Regards,

    Goodwin

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