Hello,
1.) Is it possible in real system that Master will send start address 0x01 ?
If Master wants to write only one byte at address 'h1, other addresses what ever value it has then how Master will give request?
HADDR=32'h1, HSIZE=0, HWRITE=1, HBURST=0, HTRANS=NONSEQ. Then what will happen?
2.) All transfers in a burst must be aligned to the address boundary equal to the size of the transfer. For example, you must align word transfers to word address boundaries
(HADDR[1:0]= b00), and halfword transfers to halfword address boundaries (HADDR[0]= 0). The address for IDLE transfers must also be aligned, otherwise during simulation it is likely that bus monitors could report spurious warnings.
Now Why specification hasn't mentioned about HADDR[1] in halfword and HADDR for byte?
Can anyone help me ???