Hello,
1.) Is it possible in real system that Master will send start address 0x01 ?
If Master wants to write only one byte at address 'h1, other addresses what ever value it has then how Master will give request?
HADDR=32'h1, HSIZE=0, HWRITE=1, HBURST=0, HTRANS=NONSEQ. Then what will happen?
2.) All transfers in a burst must be aligned to the address boundary equal to the size of the transfer. For example, you must align word transfers to word address boundaries
(HADDR[1:0]= b00), and halfword transfers to halfword address boundaries (HADDR[0]= 0). The address for IDLE transfers must also be aligned, otherwise during simulation it is likely that bus monitors could report spurious warnings.
Now Why specification hasn't mentioned about HADDR[1] in halfword and HADDR for byte?
Can anyone help me ???
Ajoo,
1) HADDR=32'h1, HSIZE=0, HWRITE=1, HBURST=0, HTRANS=NONSEQ
That series of control signals should ensure that 1 byte is written to address 0x1.
Yes, it is possible.
What will happen ? The slave should sample the data on the relevant byte lane (depending on bus endianness) and only update that byte in the memory map.
For a memory slave I would expect it to support all widths of transfer possible, so this byte update should always be supported, but for a peripheral device it might have specific documented transfer widths supported. If an unsupported width transfer was attempted, the slave could either return an ERROR response, or it could just overwrite the entire destination register, so corrupting adjacent bytes.
2) Now Why specification hasn't mentioned about HADDR[1] in halfword and HADDR for byte?
Because HADDR[1:0]=2'b00 and HADDR[1:0]=2'b10 are both half word aligned, HADDR[1] can have any value and still be halfword aligned.
And for byte transfers, HADDR is a byte address, so is always byte aligned.
JD
Thanks JD