1.) In AHB, When early burst termination is occurred, HRESP should be OKAY and HREADY should be high?
2.) Is there any possibilities that if write transaction is in progress and if burst is not completed then HWRITE will be low after some clock. i.e. if HWRITE is high and size is 32 and burst is INCR8, ADDR is 0x30. Then it is possible that after 4 cycle HWRITE will be low means when address is 0x40, HWRITE will be low. and if possible than what is the slave respose and HREADY?
3.) It is necessary for the master to complete the transfer completely. Master is providing address and control at each clock cycle then it is possible that master give address that is not in the range of the burst? if so than how slave respond?
Hiiii,,,
I have implemented a slave but when error response come, it will assert for one cycle only.
Can you help me how to implement two cycle error response?
Hi Ajoo,
Unfortunately I think this would be simply down to redesigning your slave state machine to go through 2 states while returning the ERROR, the first of which has HREADY low, and the second with HREADY high.
If your slave isn't state machine based, you'll need to implement a simple state machine to handle when it is returning ERROR responses.
Probably not something that can be easily described on this type of forum, and the answer too dependent on how you have currently written the slave.
JD
Thank you JD.