Hi Experts,
I have a query regarding a statement in ARM IHI0033C: Section 5.1.2 Transfer pending (Page 5-60) which states that, "When a Subordinate inserts a number of wait states prior to completing the response, it must drive HRESP to OKAY."
I am confused, in which cycle HRESP must be driven OKAY?? In the final clock cycle of the data-phase when Slave finally drives HREADYOUT HIGH after it have inserted multiple wait states by keeping HREADYOUT LOW? Or, In the previous clock cycle just before the final clock cycle? Or, In all the previous clock cycles when it was in wait states before the final clock cycle?
Please help me clarify this statement.
Thanks,
Promit