Hi Experts,
I have a query regarding a statement in ARM IHI0033C: Section 5.1.2 Transfer pending (Page 5-60) which states that, "When a Subordinate inserts a number of wait states prior to completing the response, it must drive HRESP to OKAY."
I am confused, in which cycle HRESP must be driven OKAY?? In the final clock cycle of the data-phase when Slave finally drives HREADYOUT HIGH after it have inserted multiple wait states by keeping HREADYOUT LOW? Or, In the previous clock cycle just before the final clock cycle? Or, In all the previous clock cycles when it was in wait states before the final clock cycle?
Please help me clarify this statement.
Thanks,
Promit
If the subordinate needs to add wait states it doesn't yet know if an ERROR response is needed, so at this time the HRESP response must be OKAY.
It is only once the subordinate knows that a transfer can be completed (when it could drive HREADYOUT high) that it then decides how to drive HRESP.
It could signal HREADYOUT high and HRESP=OKAY if the transfer can complete successfully, or if it wants to signal an ERROR it needs to go through the 2-cycle long ERROR response shown in 5.1.3 where HREADYOUT = low and HRESP = ERROR in the first cycle, and HREADYOUT = high and HRESP = ERROR in the second cycle.
So if the subordinate is just adding wait states while it is trying to complete the requested transfer, there is no ERROR condition, so HRESP = OKAY. It is only once the subordinate knows how it wants to respond that it could change HRESP to ERROR, with HREADYOUT needing to signal one more wait state before going high.