I used FVP_BaseR_AEMv8R to debug cortex r82 . An exception occurred after enabling dcache in SMP mode.
Any idea on where I'm doing something wrong?
1. cpu0 boot from EL2, other cpu wait cpu0 kick;
2. cpu0 change to EL1;
3. cpu0 enable MPU and dcache;
4. cpu0 kick other cpu;
5. other cpu enable MPU and dcache;
The program stopped at step3, and no exception was reported.