In the AXI protocol document, it raises unaligned access with little endian example. Per my unstanding: if I want to write to address 0x1 , bit width is 32bits. awaddr can be 0 or 0x1, wstrb must be 0xE; this is little endian.
As we know, little endian took most right bit as LSB.
What if big-endian situation? can you tell master awaddr and wstrb?
The AXI protocol supports byte-invariant endian transfers, so the same byte lanes will be used in a transfer regardless of the endianness, big or little.
So in your above example of a write to address 0x1, if AWSIZE=0x2 (32-bits), AWADDR can be 0x0 or 0x1, and WSTRB would be 0x2 (if you only want to update 0x1), or WSTRB could be 0x6 (if you want to write to 0x1 and 0x2), or WSTRB could be 0xE (if you want to write to 0x1, 0x2 and 0x3).