• State Accepted Answer
  • +1 person also asked this people also asked this
  • Locked Locked
  • Replies 14 replies
  • Answers 4 answers
  • Subscribers 88 subscribers
  • Views 3041 views
  • Users 0 members are here
Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

How to benchmark code on FVP_MPS2_Cortex-M4 simulator?

DavidAl

I need to benchmark some C++ code on the FVP_MPS2_Cortex-M4 simulator.

I considered using CMSIS function osKernelGetTickCount() to provide timestamps but the resolution of the tick timer seems to be 1ms, which is too coarse.

What would be a suitable clock counter to use for the timings?  

Would ARM_CM_DWT_CYCCNT be suitable and, if so, how would I access it?

Best regards

David

Parents
  • 0

    Hi David,

    Yes, the FVP supports this register. You can access it in your code (in Thread mode) using something like the below.

    #define CM_DEMCR               (*((volatile unsigned int*)0xE000EDFC))
#define CM_TRCENA_BIT          (1UL<<24)

#define CM_DWT_CONTROL         (*((volatile unsigned int*)0xE0001000))
#define CM_DWT_CYCCNTENA_BIT   (1UL<<0)

#define CM_DWT_CYCCNT          (*((volatile unsigned int*)0xE0001004))

void start_cyccnt()
{
    CM_DEMCR |= CM_TRCENA_BIT;
    CM_DWT_CONTROL |= CM_DWT_CYCCNTENA_BIT;
    CM_DWT_CYCCNT = 0;
}
unsigned int stop_cyccnt()
{
    CM_DWT_CONTROL &= ~CM_DWT_CYCCNTENA_BIT;
    return CM_DWT_CYCCNT;
}

    Note that the FVP is not fully cycle accurate (especially regarding memory access timing),but useful for relative comparison, See Cortex-M4 processor documentation for description of the registers.

    There are CMSIS functions available too, though these are for Arm architecture v8.1M (such as Cortex-M55), Cortex-M4 is v7-M processor, and so only supports a subset of the functionality.
    https://arm-software.github.io/CMSIS_5/Core/html/group__pmu8__functions.html

    Regards

    Ronan

Reply
  • 0

    Hi David,

    Yes, the FVP supports this register. You can access it in your code (in Thread mode) using something like the below.

    #define CM_DEMCR               (*((volatile unsigned int*)0xE000EDFC))
#define CM_TRCENA_BIT          (1UL<<24)

#define CM_DWT_CONTROL         (*((volatile unsigned int*)0xE0001000))
#define CM_DWT_CYCCNTENA_BIT   (1UL<<0)

#define CM_DWT_CYCCNT          (*((volatile unsigned int*)0xE0001004))

void start_cyccnt()
{
    CM_DEMCR |= CM_TRCENA_BIT;
    CM_DWT_CONTROL |= CM_DWT_CYCCNTENA_BIT;
    CM_DWT_CYCCNT = 0;
}
unsigned int stop_cyccnt()
{
    CM_DWT_CONTROL &= ~CM_DWT_CYCCNTENA_BIT;
    return CM_DWT_CYCCNT;
}

    Note that the FVP is not fully cycle accurate (especially regarding memory access timing),but useful for relative comparison, See Cortex-M4 processor documentation for description of the registers.

    There are CMSIS functions available too, though these are for Arm architecture v8.1M (such as Cortex-M55), Cortex-M4 is v7-M processor, and so only supports a subset of the functionality.
    https://arm-software.github.io/CMSIS_5/Core/html/group__pmu8__functions.html

    Regards

    Ronan

Children