HSELx behavior for One master to two slave transfer (back to back) for address A (slave1) and address B (slave2)

How will HSELx behave for the following Scenario?

We have one AHB master and two AHB slaves connected.

Master initiates two transactions (one after another) as follows.

1. The First transaction is for address (slave 1).  [In 1st clock cycle Address phase of A, 2nd clock cycle Data phase A]

2. The Second transaction is for address B (Slave 2). [2nd clock cycle address phase of B, 3rd clock cycle Data phase B]

My question here is:

    1. How HSELx is going to behave? Is the following correct?

          - HSEL1 will be high on the 1st clock cycle, in the 2nd clock cycle, it will be low.

          - HSEL2 will be high on the 2nd clock cycle, in the 3rd clock cycle, it will be low.   

    2. Does the address decoder sample address from the address bus at positive clock edge? or when address will change in address bus, then only it will decode that address and generate HSELx?