One master to two slave transfer (back to back) behavior for address A (slave1) and address B (slave2)

How will be behavior for the following Scenario be?

We have one AHB master and two AHB slaves connected.

Master initiates two transactions (one after another) as follows.

1. The First transaction is for address (slave 1).  [In 1st clock cycle Address phase of A, 2nd clock cycle Data phase]

2. The Second transaction is for address B (Slave 2). [2nd clock cycle address phase of B, 3rd clock cycle Data phase]

My question here is:

    - Is it allowed to start the address phase of transaction B in 2nd clock cycle?

    - My doubt is, as this address B is of slave-2, is pipelining allowed? or do we have to start the 2nd transaction after completion of the 1st transaction, which is in the 3rd clock cycle?

If it is possible to provide a timing diagram here, it will be really helpful.

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  • @Colin Campbell


    Thank you for your answer.
    I have one more question as follows.


    How will be the behavior of HSELx signal?

    In the 1st clock cycle, HSEL1 will be high, But how it will behave in the 2nd clock cycle?
    Address phase of Slave2 and the data phase of Slave1 are going on in this 2nd clock cycle.

    So in the data phase, HSELx should be high for that particular slave or not?

    Please clarify my doubt.

Reply
  • @Colin Campbell


    Thank you for your answer.
    I have one more question as follows.


    How will be the behavior of HSELx signal?

    In the 1st clock cycle, HSEL1 will be high, But how it will behave in the 2nd clock cycle?
    Address phase of Slave2 and the data phase of Slave1 are going on in this 2nd clock cycle.

    So in the data phase, HSELx should be high for that particular slave or not?

    Please clarify my doubt.

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