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Bus Matrix

Felix Varghese
Note: This was originally posted on 28th January 2009 at http://forums.arm.com

What exactly is a bus matrix? I came across the term in ARM cortex M3 specs but couldnt find any proper description. Can someone help?
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  • 0 Arm Employee Badge
    Note: This was originally posted on 28th January 2009 at http://forums.arm.com

    > so is the core the only master here and other devices are slaves?

    Yes. A master is anything which can initiate a transaction on the bus - so a CPU, a DMA engine, etc. A slave is something which recieves a transaction sent by a master (memory device, peripheral, bus bridge).

    > And what is the point of this kind of an arrangement?

    The matrix design philosophy really originated because of complex ASIC requirements, such as cellular handset designs. In these you often have 10 - 20 masters (mutliple ARM cores, DSPs, custom logic accelerators, GPUs, etc), and a large number of slaves (multiple memory ports, both on-SoC and off-SoC, and peripheral regions).

    In these designs you might have a memory slave that you want the baseband modem DSP to see, but that you do not want the GPU to be able to see. By configuring the matrix properly when you synthesize the bus, you can easily block this memory transaction simply by ensuring that the connection doesn't exist in the RTL.

    The other important thing to note is that most modern bus architectures are conceptually point to point links between individual masters and slaves. Each point to point link can have different performance characteristics if needed, such as higher priority or a wider bus width.

    For a microcontroller the "matrix" might be quite small - but the same principles apply.
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  • 0 Arm Employee Badge
    Note: This was originally posted on 28th January 2009 at http://forums.arm.com

    > so is the core the only master here and other devices are slaves?

    Yes. A master is anything which can initiate a transaction on the bus - so a CPU, a DMA engine, etc. A slave is something which recieves a transaction sent by a master (memory device, peripheral, bus bridge).

    > And what is the point of this kind of an arrangement?

    The matrix design philosophy really originated because of complex ASIC requirements, such as cellular handset designs. In these you often have 10 - 20 masters (mutliple ARM cores, DSPs, custom logic accelerators, GPUs, etc), and a large number of slaves (multiple memory ports, both on-SoC and off-SoC, and peripheral regions).

    In these designs you might have a memory slave that you want the baseband modem DSP to see, but that you do not want the GPU to be able to see. By configuring the matrix properly when you synthesize the bus, you can easily block this memory transaction simply by ensuring that the connection doesn't exist in the RTL.

    The other important thing to note is that most modern bus architectures are conceptually point to point links between individual masters and slaves. Each point to point link can have different performance characteristics if needed, such as higher priority or a wider bus width.

    For a microcontroller the "matrix" might be quite small - but the same principles apply.
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