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Bus Matrix

Felix Varghese
Note: This was originally posted on 28th January 2009 at http://forums.arm.com

What exactly is a bus matrix? I came across the term in ARM cortex M3 specs but couldnt find any proper description. Can someone help?
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    Note: This was originally posted on 28th January 2009 at http://forums.arm.com

    More modern ASIC designs have a complex N-to-M bus mapping (multiple masters, with multiple slaves, but not everything can see everything else). This assignment is a little like a matrix (rows are masters, slaves are columns, and each cell determines the visbility of that slave to that master).


    Can you ellaborate? I mean in this case we have two buses coming out of the core into the bus matrix (instruction and data), and many going out (to SRAM, peripherals, flash, etc) so is the core  the only master here and other devices are slaves? And what is the point of this kind of an arrangement?
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    Note: This was originally posted on 28th January 2009 at http://forums.arm.com

    More modern ASIC designs have a complex N-to-M bus mapping (multiple masters, with multiple slaves, but not everything can see everything else). This assignment is a little like a matrix (rows are masters, slaves are columns, and each cell determines the visbility of that slave to that master).


    Can you ellaborate? I mean in this case we have two buses coming out of the core into the bus matrix (instruction and data), and many going out (to SRAM, peripherals, flash, etc) so is the core  the only master here and other devices are slaves? And what is the point of this kind of an arrangement?
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