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AXI locked access

Note: This was originally posted on 29th May 2008 at http://forums.arm.com

Does a locked request on either the read or write channel cause both channels to be locked? For example, one master request a locked write transaction to a slave, the read channel also will be locked? if both channels have been locked, whether a read unlock access also can complete the whole locked sequence?

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0 Ben Hicks over 11 years ago

Note: This was originally posted on 6th June 2008 at http://forums.arm.com

I have ohter questions about write data channel.
1. In AXI spec 1.2.1 it said that Write data channel information is always treated as buffered, so that the master can perform write transactions without slave acknowledgement of previous write transactions.
I dont know why write data is always treated as buffered, is the interconnect must buffer all the write data to let master need not wait slave acknowledgement of previous write transactions? But I think this is not reasonable.

The buffering term is with respect to the write data channel. I.e, you don't have to receive a response for every write data transfer. Instead, the destination will "buffer" up all of the write data, and give back a single response, informing the source as to whether everything was transferred successfully or not. From a transaction point of view, you can still set the transaction to be bufferable or not by setting the AxCAHCE[0] signal.

2. In 1.3.2 there is an overlapping burst read example, but no overlapping burst write, does not allow overlapping burst write or interleave write is include overlap write already?

AXI does support the overlapping of write addresses. Proof of this can be seen when looking at the attributes of an AXI master interface, specifically the write issuing capability. It states how many active write transactions that interface can have. An active write transaction is one for which an address or item of data has been transferred, but for which a write response has not been seen. As such, if you have a write issuing capability of more than 1, you have the possibility to overlap write transactions.

Interleaving is a step on from this. A master interface's write interleaving capability is the number of active transactions for which it can send write data (from the earliest transaction). Hence, if you had a write issuing capability of 4, but a write interleave depth of 1, you could overlap all four transactions, but the data would have to appear in the order that the addresses were issued.

3. In 3.3 it said that WREADY can be asserted before AWVALID. In a mulitlayer interconnect, if AWVALID is low how the interconnect know which slave will be the desitiny? In this case is WREADY will after AWVALID but can before AWREADY?

I would imagine that an interconnect would not assert WREADY until it knows the destination. The reason for this is as you said, it will not know which slave to route that data to. I suppose an exception to this would be an interconnect that had a buffering peripheral of some kind on the slave interface. This peripheral could then hold the data until the address has been seen, freeing up the write data channel between the interconnect and the source. Remember that AXI is a point to point architecture, hence the connection from the master to the interconnect is not the same as the connection from the interconnect to the slave...although the interconnect will appear transparent to the master or slave.

I think this statement was probably included in the specification to cover the generic scenario. I.e, a simple connection from a master to a slave, between which there is no interconnect.

HTH
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0 Ben Hicks over 11 years ago

Note: This was originally posted on 6th June 2008 at http://forums.arm.com

I have ohter questions about write data channel.
1. In AXI spec 1.2.1 it said that Write data channel information is always treated as buffered, so that the master can perform write transactions without slave acknowledgement of previous write transactions.
I dont know why write data is always treated as buffered, is the interconnect must buffer all the write data to let master need not wait slave acknowledgement of previous write transactions? But I think this is not reasonable.

The buffering term is with respect to the write data channel. I.e, you don't have to receive a response for every write data transfer. Instead, the destination will "buffer" up all of the write data, and give back a single response, informing the source as to whether everything was transferred successfully or not. From a transaction point of view, you can still set the transaction to be bufferable or not by setting the AxCAHCE[0] signal.

2. In 1.3.2 there is an overlapping burst read example, but no overlapping burst write, does not allow overlapping burst write or interleave write is include overlap write already?

AXI does support the overlapping of write addresses. Proof of this can be seen when looking at the attributes of an AXI master interface, specifically the write issuing capability. It states how many active write transactions that interface can have. An active write transaction is one for which an address or item of data has been transferred, but for which a write response has not been seen. As such, if you have a write issuing capability of more than 1, you have the possibility to overlap write transactions.

Interleaving is a step on from this. A master interface's write interleaving capability is the number of active transactions for which it can send write data (from the earliest transaction). Hence, if you had a write issuing capability of 4, but a write interleave depth of 1, you could overlap all four transactions, but the data would have to appear in the order that the addresses were issued.

3. In 3.3 it said that WREADY can be asserted before AWVALID. In a mulitlayer interconnect, if AWVALID is low how the interconnect know which slave will be the desitiny? In this case is WREADY will after AWVALID but can before AWREADY?

I would imagine that an interconnect would not assert WREADY until it knows the destination. The reason for this is as you said, it will not know which slave to route that data to. I suppose an exception to this would be an interconnect that had a buffering peripheral of some kind on the slave interface. This peripheral could then hold the data until the address has been seen, freeing up the write data channel between the interconnect and the source. Remember that AXI is a point to point architecture, hence the connection from the master to the interconnect is not the same as the connection from the interconnect to the slave...although the interconnect will appear transparent to the master or slave.

I think this statement was probably included in the specification to cover the generic scenario. I.e, a simple connection from a master to a slave, between which there is no interconnect.

HTH
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