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AXI locked access

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Note: This was originally posted on 29th May 2008 at http://forums.arm.com

Does a locked request on either the read or write channel cause both channels to be locked? For example, one master request a locked write transaction to a slave, the read channel also will be locked? if both channels have been locked, whether a read unlock  access also can complete the whole locked sequence?
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    Note: This was originally posted on 5th June 2008 at http://forums.arm.com

    Thank you, I have got more clear about LOCKED access.

    I have ohter questions about write data channel.
    1. In AXI spec 1.2.1 it said that Write data channel information is always treated as buffered, so that the master can perform write transactions without slave acknowledgement of previous write transactions.
    I dont know why write data is always treated as buffered, is the interconnect must buffer all the write data to let master need not wait slave acknowledgement of previous write transactions? But I think this is not reasonable.

    2. In 1.3.2 there is an overlapping burst read example, but no overlapping burst write, does not allow overlapping burst write or interleave write is include overlap write already?

    3. In 3.3 it said that WREADY can be asserted before AWVALID. In a mulitlayer interconnect, if AWVALID is low how the interconnect know which slave will be the desitiny? In this case is WREADY will after AWVALID but can before AWREADY?
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  • 0
    Note: This was originally posted on 5th June 2008 at http://forums.arm.com

    Thank you, I have got more clear about LOCKED access.

    I have ohter questions about write data channel.
    1. In AXI spec 1.2.1 it said that Write data channel information is always treated as buffered, so that the master can perform write transactions without slave acknowledgement of previous write transactions.
    I dont know why write data is always treated as buffered, is the interconnect must buffer all the write data to let master need not wait slave acknowledgement of previous write transactions? But I think this is not reasonable.

    2. In 1.3.2 there is an overlapping burst read example, but no overlapping burst write, does not allow overlapping burst write or interleave write is include overlap write already?

    3. In 3.3 it said that WREADY can be asserted before AWVALID. In a mulitlayer interconnect, if AWVALID is low how the interconnect know which slave will be the desitiny? In this case is WREADY will after AWVALID but can before AWREADY?
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