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applications of amba axi

abilash abilash
Note: This was originally posted on 7th February 2007 at http://forums.arm.com

hello, i have read the whole of the axi protocol. i would like to know the applications of the protocol. is it anywhere used in the real time applications or some specific devices. if any please do tell me.
i would also like to know the advantages of axi protocol over the conventional data transfer protocols. please give details...

thanks... with regards....
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    Note: This was originally posted on 21st February 2007 at http://forums.arm.com

    "supporting write data interleaving"

    (this is defined in section 8.5 of the AXI spec.)  something else that may be helpful is to take a look at the documentation for the AXI memory controller and interconnect generator.  write data interleaving is a performance enhancement for interconnects that are combining multiple write streams from different masters.  in some specs, like AHB, burst writes are atomic and do not allow interleaving.   but, that means a slow master could block the bus for an extended period of time.  in AHB, perhaps the split-retry mechanism somewhat allows very coarse-grained data interleaving at expense to the master.

    consider a DMA controller on AHB that was writing into an AXI memory controller.  it's possible that with width conversion, or clock frequency crossing, that the DMA controller would write 1 word on AXI every few cycles.  interleaving would allow the interconnect to allow the ARM processor to write to the AXI memory controller in those gaps between words of the slow burst. 

    the most likely case of interleaving occuring is from the interconnect, which is aggregating writes from multiple masters.  an ARM processor doesn't  interleave its write data (write interleave depth of 1).  also, not all slaves can support data interleaving, although ARM's memory controller documentation says it supports interleaving.  the interconnect allows you to indicate the interleave depth per port.  while interleacving optimizes bus bandwidth in the presence of slow masters, it probably means you have to have quite a bit of buffering in your memory controller to support the different streams of data.

    "no defined timing relationship between address and data transfers"

    (take a look at section 3.2)  this is a little bit funny, but there's a seperate write address and write data channel (in addition to the write response channel).  the write address and write data channel's independently handshake, and the order is not defined.  i think a possible scenario would be that because there's only 1 address transfer per burst write, if you had back to back burst writes, it's possible you could request both addresses before you finished the data transfers of the first request.  i'm not sure when a "real" master would request the data before requesting the address channel for a write request, although it's possible that the interconnect causes ordering differences, depending on the route each channel gets.

    "ability to add register slices to ease critical timing paths"

    ARM's AXI interconnect is completely combinational, i believe.  this doesn't scale well by itself.  so, if you have a large interconnect, you probably need to add some pipeline registers at the ports of the interconnect to meet your timing goals, assuming you want high speed.  the implication of "register slices" is that you can simply add registers along the channels, rather than creating  true AXI staging blocks with a slave and master port, which would have to actually arbitrate along each stage and probably involve some buffers and state machines. 

    i've got a bit of question on this, too, which is: does ARM have an AXI regsiter slice prime cell?  or is it really just valid to add registers along a channel?  can the "valid" and "ready" signals both have registers?  also, is there a recommended timing specification for AXI masters and slaves (that aren't interconnects)?
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  • 0
    Note: This was originally posted on 21st February 2007 at http://forums.arm.com

    "supporting write data interleaving"

    (this is defined in section 8.5 of the AXI spec.)  something else that may be helpful is to take a look at the documentation for the AXI memory controller and interconnect generator.  write data interleaving is a performance enhancement for interconnects that are combining multiple write streams from different masters.  in some specs, like AHB, burst writes are atomic and do not allow interleaving.   but, that means a slow master could block the bus for an extended period of time.  in AHB, perhaps the split-retry mechanism somewhat allows very coarse-grained data interleaving at expense to the master.

    consider a DMA controller on AHB that was writing into an AXI memory controller.  it's possible that with width conversion, or clock frequency crossing, that the DMA controller would write 1 word on AXI every few cycles.  interleaving would allow the interconnect to allow the ARM processor to write to the AXI memory controller in those gaps between words of the slow burst. 

    the most likely case of interleaving occuring is from the interconnect, which is aggregating writes from multiple masters.  an ARM processor doesn't  interleave its write data (write interleave depth of 1).  also, not all slaves can support data interleaving, although ARM's memory controller documentation says it supports interleaving.  the interconnect allows you to indicate the interleave depth per port.  while interleacving optimizes bus bandwidth in the presence of slow masters, it probably means you have to have quite a bit of buffering in your memory controller to support the different streams of data.

    "no defined timing relationship between address and data transfers"

    (take a look at section 3.2)  this is a little bit funny, but there's a seperate write address and write data channel (in addition to the write response channel).  the write address and write data channel's independently handshake, and the order is not defined.  i think a possible scenario would be that because there's only 1 address transfer per burst write, if you had back to back burst writes, it's possible you could request both addresses before you finished the data transfers of the first request.  i'm not sure when a "real" master would request the data before requesting the address channel for a write request, although it's possible that the interconnect causes ordering differences, depending on the route each channel gets.

    "ability to add register slices to ease critical timing paths"

    ARM's AXI interconnect is completely combinational, i believe.  this doesn't scale well by itself.  so, if you have a large interconnect, you probably need to add some pipeline registers at the ports of the interconnect to meet your timing goals, assuming you want high speed.  the implication of "register slices" is that you can simply add registers along the channels, rather than creating  true AXI staging blocks with a slave and master port, which would have to actually arbitrate along each stage and probably involve some buffers and state machines. 

    i've got a bit of question on this, too, which is: does ARM have an AXI regsiter slice prime cell?  or is it really just valid to add registers along a channel?  can the "valid" and "ready" signals both have registers?  also, is there a recommended timing specification for AXI masters and slaves (that aren't interconnects)?
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