• State Not Answered
  • Locked Locked
  • Replies 6 replies
  • Subscribers 89 subscribers
  • Views 21638 views
  • Users 0 members are here
Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

AMBA AXI Write response

Sai Krishna
I am just going through the specs of AMBA AXI.
I've few questions.It will be great if anybody clarify
1) Why there was no Write response for each beat in burst Write. But there is a seperate Read response for each beat in a Read burst ?
2) How to terminate A read/write burst ? Specification says we can not stop bursts intermittantly.
         i) Can A master can give WLAST in middle of a burst transfer ?
         ii) in the same way if slave assersts RLAST before the completion of a busrt read?
If WLAST and RLAST can not do the above cases, then what is the special use of WLAST and RLAST because we are getting individual beat responses anyway?
3) Whats the exact use of Exclusive Read and Write Pair transaction? Where exactly these will be used?

Thanks in advance..
Regards,
Sai Krishna
Parents
  • 0
    Note: This was originally posted on 30th January 2007 at http://forums.arm.com

    Hi,
    I have few more questions,
    1) In "Multi-layer AHB overview" document in Page 4 it says " When a layer is waited an Input Stage is used to store a copy of the pipelined address and control information until the access to the shared slave is given." Why does this need? Because The master anyway extend the address/data/control what ever been there when HREADY goes low( Which is actually driven by the Interconnect/slave to that particular lost master ) in AHB lite.
    2) In Multiple slaves appearing as a single save topology, How does any master knows the response from which of those connected slaves.

    Thanks in advance
    sai krishna
Reply
  • 0
    Note: This was originally posted on 30th January 2007 at http://forums.arm.com

    Hi,
    I have few more questions,
    1) In "Multi-layer AHB overview" document in Page 4 it says " When a layer is waited an Input Stage is used to store a copy of the pipelined address and control information until the access to the shared slave is given." Why does this need? Because The master anyway extend the address/data/control what ever been there when HREADY goes low( Which is actually driven by the Interconnect/slave to that particular lost master ) in AHB lite.
    2) In Multiple slaves appearing as a single save topology, How does any master knows the response from which of those connected slaves.

    Thanks in advance
    sai krishna
Children
No data