I'm running a baremetal EL2 program downloaded from Development Studio(DS) to the Morello hardware (which already has a branch-to-self loop running compiled as BL33 in the fip). I've modified the initialisation scripts to run at EL2 as per https://community.arm.com/support-forums/f/morello-forum/52923/baremetal-tfa-payload-built-for-capability-mode-still-in-pstate-a64-on-el2-entry and have a single c file with my main function. This works fine on the FVP when downloaded via DS, but when I download to the hardware and step through the code from entry it seems to stop after the first few instructions of crt0 on the HLT #0xF000 instruction which I believe is part of the Angel debug - AngelSVCAsm AngelSVC.
AngelSVCAsm AngelSVC
On the FVP this instruction populates the memory with the heap and stack addresses.
So this explains why when I by-passed HLT #0xF000 by moving on the program counter, it falls over on the first use of the stack. It looks like there is no stack address value stored in memory, the code that reads the value reads in zero and hence causes a problem later.
What do I need to do differently to make it work on the hardware? as apposed to FVP?, is there a build setting I need to include?
Many thanks
I've been looking at this issue on and off for a while and have now found a solution to the problem so wanted to share it here, and hope it helps others.
I found that adding cache flushing instructions ( isb ) to the modified crt0.S file (to run at EL2) before switching into capability mode resolved all the issues I had with trying to run capability code on the hardware.This might explain why stepping through the code worked, but running the code did not.
Specifically I found I needed two of these instructions placed here as follows in crt0.S:
//MODIFIED***comment out for EL2 //mrs x0, SCTLR_EL3 //bic x0, x0, #(1 << 20) /* clear CD0 */ //bic x0, x0, #(1 << 22) /* clear CD */ //msr SCTLR_EL3, x0 //ADDED ISB HERE needed to avoid WFI B cpu hang isb //MODIFIED***modify for EL2 /* Use c28 as the adrdp base, no DDC/PCC offsetting and seal CLR */ mov x0, #(1 << 4) | (1 << 7) msr CCTLR_EL2, x0 //ADDED ISB HERE needed to avoid WFI B cpu hang isb#endif //MODIFIED***comment out for EL2 //mrs x0, CPTR_EL3 //bic x0, x0, #(1 << 10) /* clear TFP */ //msr CPTR_EL3, x0#ifdef __ARM_FEATURE_C64 /* Switch to C64 mode. */ READSYS c1, DDC /* Default data capability */
Also just to add, it looks like this has been fixed in release 1.4