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FIOSET and FIOCLR strange behaviour (at least in the emulator)


    // Set initial conditions:
    // Both MCLR pins (Feature2 and Feature5) High
    // PGD and PGD pins Low
    LPC_GPIO0->FIOSET = (1<<23) | (1<<26);    // Set MCLR pins high
    LPC_GPIO0->FIOCLR = (1<<2) | (1<<3) | (1<<24) | (1<<25);    // Set PGC and PGD pins low

I don’t *think* that setting of FIOCLR should change any pins except P0.2, P0.3, P0.24 and P0.25!



Most odd!  I never set P0.23 or P0.26 to anything other than HIGH but the LA trace shows both going LOW then HIGH.???????

Any thoughts?  (yes I searched the code for FIOSET, FIOCLR and FIOPIN)