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Hi,
I am trying to port a library that is working with FreeRTOS to RTX. The microcontroller is the same: STM32F4. The library uses critical sections. I have tried using the same implementation for the critical section for RTX as for FreeRTOS(BASEPRI) but I often end up in UsageFault. I know that RTX uses extensively the SVC in the code.
Could it be that the Critical sections should be implemented differently ? Do you know of any other differences between FreeRTOS and RTX that could cause problems?
Best regards, Sebastian
I have just been looking into the options of protecting sections of code (atomic) when using the Cortex M0+ family.
Googling around there appear to be two approaches:
(1) Interrupt (SVC)
(2) Software (PRIMASK)
At the moment I have used the software (2) approach based on discussion:
www.mcuoneclipse.com/.../
__attribute__((always_inline)) __INLINE uint32_t critical_Enter (void) { uint32_t primask; primask = __get_PRIMASK(); __disable_irq(); return primask; } __attribute__((always_inline)) __INLINE void critical_Exit (uint32_t primask) { __set_PRIMASK (primask); }
Keil appears to use both of these approaches within RTX.
What are the merits / trade-offs for each approach?
"I have just been looking into the options of protecting sections of code (atomic) when using the Cortex M0+ family."
You mean protecting sections of data - not code !
Yes, poor choice of word...I meant protecting data. Any opinion on why and when to use SVCs instead of s/w (PRIMASK) for Cortex-M0.