I'm trying to write unit tests for non-executable SRAM. As a step in that process, I try to execute code inside SRAM by putting some Thumb opcodes in RAM and then executing them. The opcodes execute fine if I put a tiny delay (~10 millisecs) before executing them. If I don't put any delay then I get imprecise bus access fault, i.e. there is a hard fault and fault register values are:
HFSR = 0x4000.0000 CFSR = 0x0000.0400
Other things to note are:
- The code runs under RTX.
- I have not set any MPU settings. If I'm correct, the defaults allow RWX access to privileged mode. All my code runs in privileged mode.
- The same code runs without any faults on Cortex M4
Any pointers about how to investigate this further will be very helpful.
Thanks!
Might the processor need time to flush the data before you call the code and starts to fill the pipeline? Self-modifying code must take into account the pipeline and caching for lots of newer architectures.