Hi all,
I have a C51 application that requires the following operation which is close to a reset but it is not a reset:
1. when a bit is set in a register, call a function and return 2. when a bit is cleared in a register, exit the ISR and jump back to the main routine (the stack should be reset).
I use Keil C51 and uses the following method trying to achieve the aims but to no avail:
void isr(void) interrupt { if (register & bit) function1(); else #pragma asm ljmp 800H; // 800h=main routine address #pragma endasm }
I tried this routine but it seems that the code is stuck. Has anybody tried a similar implementation, or is there anything that I can do to implement such a scheme?
Thanks very much for your response and Best Regards.
William
Hi,
I have had to use a technique that might be similar, whereby an ISR was required to trigger a processor reset.
For this it was necessary to carry out:
LJMP 0000h
The stack, and most everything else, was reset as a consequence and the main routine was re-entered.
If this is similar, then you will have to be careful of a number of special actions that are required if the jump to the startup is going to be successful on every attempt - But that would be the next step.
Ignore Erik's refound silliness!
Asuming the reason for the requirement is appropriate and justifiable - You, as a programmer of an embedded system, should always be prepared to interpret the rules in a manner that allows the task to be done in a manner that works as the requirement needs.
what a piece of ultimate CRAP. The SFRs will not be reset, the Interrupt flags will not be reset, the ... will not be reset. E.g. if you search, you will find that you have to calculate the number of stacked interrupts and issue a correcponding number of RETIs before the LJMP and still the SFRs etc will not be reset.
If you want to trigger a reset there is ONE way: activare watchdog while (1) or jmp $
I suggest you, instead ignore the self admitted "Silly".
Erik
Erik, I think you should let people get a bit of rope if they want to. If they want to hang themselves, it's their choice. If they are really good with ropes, maybe they manage some nice knots instead :)
Yes, there are limitations to jumping to the reset vector. Some startup code survives it, some doesn't. It will not reset any locked-up hardware, but with a bit of luck, the application will behave as after a reset.
In this case, I think it is enough to warn people about the problems, and let them be big boys and decide if they can live with the remaining problems.
The watchdog method only works if you have a watchdog. And in some situations you may have one but not be able to use it. If you for example power your processor from the phone line, the extra power consumption from the watchdog may be the difference between a working and a non-working solution.
Erik should REALLY learn to interpret complete sentence before being so silly!
I said:
"... then you will have to be careful of a number of special actions that are required if the jump to the startup is going to be successful on every attempt"
Contrary to what YOU say (or might think) there are other ways! I've done it!
Go, be daring and try something new:
Don't be so silly!
Hello,
I am making a project where I need to use 14 outputs. I choose for that the entire Port 1 pins, P3.2, P3.3, P4.4, P4.5, P4.6 and P4.7. But I have a problem with that last four. They are part of the Port 4 and can function as general I/O or in its alternate function as address pins A16, A17, A18, and A19. Here is where my problem is. I can’t configure them to work as I/Os. I have read about configuring that in an assembler source called startup.a51 by the SFR registers P4CNT, P5CNT, P6CNT, MCON and MCON1. I have found different versions of that source file and tried a lot of different combinations in that registers, but I don't achieve what I want.
For all that, I would be very grateful if someone can explain me how to do it or can reply me with an example of the startup file configured correctly.
Best regards,
Gorka
1) DO NOT hijack a thread on a differnt subject, start a new thread 2) NOBODY can help you if you insist on keeping it a secret which derivaitive you use.
Is this possible if we really use hard reset (Logic 1 Pulse with some delay) by using ISR and a Port Pin Connected to RESET Pin? so that Controller can RESET itself by Applying RESET signal by ISR. I mean Software *** Hardware RESET!
Note This message was edited to reduce width.
That's one way to get a real hardware reset.
However, driving your own RESET pin directly from an I/O port pin on the same device brings up a somewhat tricky question of stability. The port pin only pulls the reset line down because it was programmed to do so. Resetting the processor resets the I/O ports, so they can no longer drive RESET low. (If the pins can drive RESET low while they are reset, then you can't come out of reset!)
What does the RESET line do while the I/O pin gets reset? Does it stay stable long enough actually to RESET properly? If so, is that behavior guaranteed by the design, or are you just getting lucky?
You might need some slightly more complicated hardware outside the processor to guarantee the stablity of this transition. There are chips made to perform exactly this function. The I/O pin would tell the supervisor to reset the CPU; the supervisor would pull the RESET line.
Here's an app note for one such supervisor chip. www.intersil.com/.../AN1230.pdf This one has some built-in EEPROM, so it has a serial interface and is slightly more complicated that what you need. But notice the way the I/O pins are connected to the supervisor, which in turn is connected to the RESET line.
AT89S52 can be reset with logic high for 2 machine cycles to RESET PIN. I used Proteus VSM 7.1 and it shows RESET... Reset itself by ISR and Port Pin
delay(); RESET_Port_Pin=1; //Soft Reset to uC by Port Pin delay(); RESET_Port_Pin=0; delay();
But in Actual Circuit this Doesn't works. Without any chip it could be done or not? I think momentry latching of some type will help?