Hi, Based on the Phytec example code for external nor flash bootloader, i see that they are copying code from the external nor flash to the external SDRAM and starting it by pointing a function pointer to the external sdram.
My first doubt is: Since the target options specifies the off chip ROM1 at address 0xE0000000, and EMC has been enabled in the startup file,does this secondary bootloader code go directly to the external nor flash at address 0xe0000000 when loaded from keil uvision?
Second doubt: Does this secondary bootloader(if present in ext nor flash), cause a copy of the application code from user program offset to the ext sdram and pass function pointer to execute it from sdram when powered up?
Third doubt: In target options>>Debug, what is the purpose of Debug_Boot.ini?
Guys please be patient with me..I am very new to this and have a lot of doubts about this topic
Thanks :)
Have you asked Phytec ?
" ... Phytec example code for external nor flash bootloader, i see that they are..."
For doubts about what Phytec have done, you should be asking Phytec !
In an ideal world, that might be the case. But this is not an ideal world. My previous experience with them and questions given was not great.
Anyway, this is not Phytec specific, it is really more related to the LPC3250.
When booting from NOR flash, it is not necessary to copy the code to RAM and run it from there. In fact, the internal CPU boot code executes in place (i.e., from the NOR).
If booting from NAND, a copy of code to internal RAM and execute from there is required.
The startup code would initialise the use of SDRAM if required. The necessary initialisation is of course specific to the board.
It's a long time since I looked at the Phytec supplied code, but I don't remember seeing a copy of code as you describe for NOR. I do remember it for NAND.
Chapter 35 of the LPC3250 user manual gives the best (and probably most accurate) description of the boot process.
This is copy of what Phytec code is doing:
int main (void) { unsigned long *src, *dest; long size;
size = (*(( long *) (EXT_NOR + USER_PROG_OFS + 0x14))); src = ((unsigned long *) (EXT_NOR + USER_PROG_OFS)); dest = ((unsigned long *) (EXT_SDRAM));
if (size == 0xFFFFFFFF) while (1); // If no user program size information if (size == 0xE1A00000) // Unknown size (NOP instruction) size = MAX_USER_PROG_SZ;
memcpy (dest, src, size); // Copy user program to Extarnal SDRAM AppEntry(); // Start the user Application return (0); }
So were my doubts right or wrong??? Please do clarify.
The code can be found at <Dir where keil has been installed>:/Keil/ARM/Boards/Phytec/LPC3250/Bootloader_NOR
I already did. Regardless of what Phytec are doing, the LPC3250 user manual states what happens.
The .INI files typically program chip register to get the part in a desired configuration to run the code. Often this replicates startup code configuring external buses, and memories. Review the content of the .INI, and review the Reference Manuals for your part and board. Reading documentation and understanding it tends to alleviate doubt.
If you want to see what the code is doing, suggest you unclick "Run to Main" and step through it, and open memory windows so you can see what's where.
In systems with NAND memory you can't run the code in-place, you have to initialize memory buses for hardware unique to your board, and then copy the data into a memory which will permit in-place execution. The compiler/linker need to built that code for the location it will ultimately run at, and the loader may store it somewhere else can copy it into place before transferring control to it.
Just a wierd idea:
If i convert my application code to an equivalent binary in a header file(using bin2h.exe) and then directly load my nor flash boot loader code along with my header file containing the binary values of my application code at start address 0xe0000000 under target options for off chip rom,my code directly goes into the not flash along with my boot loader code. Then i can set PC=0xe0000004(boot loader program offset) in debug.ini file so tht my code executes boot loader in nor flash on power u(which contains my application code)
Sorry, but have you now read what I suggested? It is not a particularly long chapter and it has all the necessary information you should require. It's what I used successfully for booting from both NOR and NAND.