Using uvision4 to build project for Cortex-M3. When I look at assembly listing I notice that the __schedule_barrier() call generates two NOPs instead of using one of the ARM memory barrier instructions. Is this correct?
Thanks
The __force_stores(), __memory_changed() and __schedule_barrier() intrinsics only effect the compiler's view of the world. Somewhat suprisingly they don't generate any barrier instructions.
I also happend to notice these related Knowledge Articles:
- In what situations might I need to insert memory barrier instructions? <infocenter.arm.com/.../ka14041.html>
- Does Cortex-M3 need Memory Barrier instructions? <infocenter.arm.com/.../ka13593.html>
- Why are barrier instrinsics not documented in the compiler documentation? <infocenter.arm.com/.../ka14552.html>
Hi Scott,
Somewhat more surprising is the fact that a memory barrier intrinsic does not imply a preceeding __force_stores() behavior. In a particular case, the compiler scheduled the critical memory access after the the memory barrier rendering the latter practically useless. This may have changed since I raised a support case about this although I was told back then that there were valid use cases for the observed behavior (w/o giving an example).
Regards Marcus http://www.doulos.com/arm/