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Hardening of firmware

Here is a link to a number of suggestions I have compiled for hardening of firmware.

I'm pretty sure that a lot can be said about the list, so please post coding tips or links to pages with good information of software hardening.

iapetus.neab.net/.../hardening.html

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  • The reason I did pick that example was because Jack has a pre-chewed policy document for how to develop software (where to store source, how to indent, ...) on his page. One of the things it mentions is to be careful about malloc() defragmentation and to check if malloc() has support for garbage-collect of free space.

    It can be done using dual indirection (segmented MMU like in 286 or explicit handles like used in several OS from before MMU) or by instrumenting the source code to allow the stack and data structures to be walked - 16-bit Windows for example has special progolgue/epilogue for all functions, so that Windows can patch the return addresses on the stack when a memory block has been moved.

    But I haven't seen anyone trying to take this to the embedded world because of the big problems with deterministic response times. So I wonder if Jack did add that part by accident, or if he really had specific usage cases with such memory managers in the embedded world.

    In the end, it is normally way easier to write the application to use fixed-size memory blocks that can be allocated/released without any fragmentation. Most RTOS has thread-safe allocation functions that can work with arrays of such memory blocks. And when the requirements gets higher, or the work with specifically rewriting the code is decided to increase the complexity too much, then a processor with MMU and paged memory will work well, as long as all dynamic allocations are made for a number of pages instead of using a variable-size scheme like malloc() normally uses.

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  • The reason I did pick that example was because Jack has a pre-chewed policy document for how to develop software (where to store source, how to indent, ...) on his page. One of the things it mentions is to be careful about malloc() defragmentation and to check if malloc() has support for garbage-collect of free space.

    It can be done using dual indirection (segmented MMU like in 286 or explicit handles like used in several OS from before MMU) or by instrumenting the source code to allow the stack and data structures to be walked - 16-bit Windows for example has special progolgue/epilogue for all functions, so that Windows can patch the return addresses on the stack when a memory block has been moved.

    But I haven't seen anyone trying to take this to the embedded world because of the big problems with deterministic response times. So I wonder if Jack did add that part by accident, or if he really had specific usage cases with such memory managers in the embedded world.

    In the end, it is normally way easier to write the application to use fixed-size memory blocks that can be allocated/released without any fragmentation. Most RTOS has thread-safe allocation functions that can work with arrays of such memory blocks. And when the requirements gets higher, or the work with specifically rewriting the code is decided to increase the complexity too much, then a processor with MMU and paged memory will work well, as long as all dynamic allocations are made for a number of pages instead of using a variable-size scheme like malloc() normally uses.

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