Hi, I am jang-hyun Son, a college student from South Korea.
I will study Mali GPU with OpenCL, and before that, I am now studying about the Mali G71 architecture.
My question is that, Why are there multiple(actually 4) L2 Caches in the image above.
I think only one L2 cache is used for one GPU normally.
Thank you for reading my question, and i wish you a reply.
It is a single logical cache implemented in multiple physical parallel slices. The number of cache slices used in a design increases as the number of shader cores increases, allowing more parallel reads and writes as the bandwidth requirements of the design increase (as all cache slices can be accessed in parallel).
HTH, Pete
Thank you very much.
Then, one more question comes to my mind. I found AMBA 4 ACE is used for cache coherency.
Because of the multiple L2 caches, is it required to put AMBA 4 ACE under each of L2Cs for L2 cache coherency?
I am sorry for multiple questions, and thank you again.
The external memory interface can be coherent using ACE (silicon partner implementation choice - it's optional). All cache slices behave a single logical cache, so must correctly handle ACE irrespective of the number of slices.