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Register allocation

Hi Forum,

I was playing around with the number of interactions in a  loop for a shader which initially reported 32 WR and 54 UR registers by malioc.

As the number of iterations increased the number of allocated UR kept on increasing to 58,60,64 and so on whereas the WR number remained 32.

What is the reason for this behaviour? Since according to the use case of UR, we generally don't expect constants and uniform data to increase as the number of iterations increase.

Regards,

Swapnil

Parents
  • Hard to be certain without seeing the code - the refactored code needing more constants (including compiler generated ones, like address offsets), or having more ability to promote loads to uniform registers are the two most likely options. 

    Cheers, 
    Pete

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  • Hard to be certain without seeing the code - the refactored code needing more constants (including compiler generated ones, like address offsets), or having more ability to promote loads to uniform registers are the two most likely options. 

    Cheers, 
    Pete

Children