This discussion has been locked.

You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Is there any cache coherence between Mail400 and CPU

Hi all. As you know, there is cache in Mail400 and A35 seperately. Do I need to implement hardware cache coherence between them, for example, using CCI.

Top replies

Peter Harris over 2 years ago in reply to asic_xuan +2 verified

Mali-400 doesn't support the CCI hardware coherency protocols, this is only supported in the Bifrost architecture onwards. Any required cache coherency is managed manually in software by the device driver...

Parents

0 asic_xuan over 2 years ago in reply to Peter Harris

Hi Peter, could I raise another question? For Mali G31 and Cortex-A35, can I still use software to maintain the coherency between them?

I see a figure presented by ARM, which display a system with A55,D51,V52,G31 and NIC450. From this figure, it seems there is no need to implement hardware coherency between mali and cpu.Will the management by software affect the performance?
Cancel
Up 0 Down

Cancel

Reply

0 asic_xuan over 2 years ago in reply to Peter Harris

Hi Peter, could I raise another question? For Mali G31 and Cortex-A35, can I still use software to maintain the coherency between them?

I see a figure presented by ARM, which display a system with A55,D51,V52,G31 and NIC450. From this figure, it seems there is no need to implement hardware coherency between mali and cpu.Will the management by software affect the performance?
Cancel
Up 0 Down

Cancel

Children

No data