Hey,
on our development board we use PCIe to exchange data between the two Tegras on a NVIDIA Drive PX2.
Basically the data coming across NT ports acts like a DMA engine writing to system RAM. With an interface function from the API of the PCIe-chip we allocate memory. In its definition the API-function uses "dma_alloc_coherent" from the Linux kernel. In our application we now can use the address of the allocated memory area and do our work. With memory barriers the right order of execution between reads/writes is guaranteed.
We are facing the problem, that (how it looks) new data is not polled out of the RAM and we read old data from the CPUs cache. Unfortunately the MMU is disabled, as we can't use the PCIe-driver when it is activated.
I have come across this document about Cache coherency but I am not exactly sure, if this can help us. In addition I am a complete newbie with programming on ARM on such a low level.
Any help is appreciated, thanks in advance.
Jan
It doesn't seem possible the data caches are active without the MMU and data cache enabled. Without MMU on you may only cache the instructions if enabled. All the controls are in sctlr of each of the exception levels but EL0.
I think I saw a case in which MMU and data cache got disabled without clean, invalidate or clean&invalidate in which then data cached got retained in the cache and active upon MMU and data cache re-enable and messed with the memory but it was due to bad coding.