why okay response is single cycle?but error,split,retry is two cycle.why?
Because SPLIT, ERROR and RETRY involve the master having to cancel the next indicated address phase transfer before it can be sampled by a slave when HREADY is high at the end of the data phase of this transfer.
It takes one cycle of the data phase for the master to see that the response is not OKAY, and then in the second cycle it can change HTRANS to signal an IDLE transfer instead of the address phase it was signalling. Synchronous logic requires that this occurs over 2 cycles, the first to sample HRESP and the second to then modify HTRANS.
If you did NOT cancel the next indicated address phase transfer, the selected slave would then sample that next transfer, resulting in the master performing transfers out of order to what it intended (it hasn't yet successfully performed the transfer that received the non-OKAY response).
Note that the master can choose to continue with the next indicated address phase transfer if the response is ERROR (although this would still happen with a 2 cycle ERROR response timing), but the master MUST cancel the next indicated transfer if the response is RETRY or SPLIT.