Hello,
In Cortex, A9 CPU register CPSR tells the current execution mode , bit M[3;0]
I am looking for if there is similar register present in A64 architecture .
Reading ESR_EL3/EL2/EL1, I think this is difficult to determine, if system in IRQ mode or not
regards
AArch64 doesn't have a direct equivalent of IRQ mode.
You can read the current EL from PSTATE, which is the rough equivalent of the CPSR but this will just tell you you are in EL1. EL1 kind-of maps to kernel space, it is where you will probably branch to when taking an IRQ exception but it is not just for IRQ handling.