HI...
A)
1). I am now using a continuously 10 transfer of the SINGLE BURST write based read transfer. In spec says the default ready signal is HIGH.
2).First thing i complete the first transfer of the write based read operation.
3). Then it takes the busreq for one clock,grant for one clock and one extra clock.After the second transfer is started.
4). In between the first and second transfer the HREADY will be should be low or HREADY should be high.
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B) This is another
I am using the AHB lite.
clk1 clk2 clk3 clk4
trans=2 trans=2 trans=2 add(A) add(A) write-data(A)
read_data(A)This is the lite spec. so the single master single slave.
1)This is single transfer so trans=2. First the i am write the write_data(A),At the time the time trans also maintained in clk2.
2)/Again i am read the same address the value read_data(A), This is also trans maintained in clk3.
This correct or not.
Hi,
The AHB-lite protocol mentioned in your subject line does not have HBUSREQ and HGRANT arbitration signals, so your description in step 3 of question A does not apply. Can you confirm if it is AHB or AHB-lite that you are using ?
Assuming it is AHB, and not AHB-lite, when your master is not granted the bus, something else will be driving transfers, and HREADY will be driven by the slave addressed by that master.
If this other master, or your master if it remains granted during this time, is signalling IDLE transfers, the protocol requires that HREADY is driven high as IDLE transfers do not have any associated data transfer that the slave would need to add wait states to complete.
So in every bus cycle there will be one master granted control of the bus, and the slave selected for each address phase transfer wll respond in the data phase of each transfer by driving HREADY and HRESP as required for that transfer.
B)
The sequence you describe is a master performing back-to-back write and then read transfers. For this sequence HREADY would have been high in cycle 2 to allow the write transfer data phase to complete in one cycle, and similarly it was presumably high in cycle 3 to allow the read transfer data phase to complete in one cycle.
You show HTRANS driven to NONSEQ in cycle 3, so cycle 4 would be the data phase transfer of that 3rd NONSEQ access. If you only wanted to perform a single write followed by a single read, HTRANS would have signalled IDLE in this 3rd clock cycle.
So nothing wrong with the sequence you show.