As stated in GIC v3 Arch: After powering up a PE, software must set ProcessorSleep to 0 and wait until ChildrenAsleep == 0.
Can you please also state the conditions for GICR_WAKER.ChildrenAsleep to go 0? As in my case at a particular operating frequency of GIC500, for some ARM A53 cores ChildrenAsleep do not go to 0 indefinitely (post clearing ProcessorSleep).
And hence respective cores do not come out of WFI.
P.S. Interrupt targeted to the Core and PE clocks enabled with WakeRequst signal.
Thanks Martin, Ryan
Yes you're correct, the GICR_WAKER is written by another PE of the device.
Also, in the later set of experiments I found that clock was still gated to the Core cluster which may explain why this handshake never completed. In the SoC design, the wake_request signal propagates to the COP and directs it to re-enable the clocks of the core cluster. Seems the wake_request signal never reached the COP boundary, is there some way in GIC500/CPU interface/memory mapping where I can look for the status of this signal (per core)?
Regards,
Danish