Hi,
I am verifying a low complexity RTL design having AX Iinterface. I am working on this AXI master connected with AXI VIP slave interface. I see that in a few scenarios, when AXI master timesout, the WLAST signal is not generated at the master interface eventhough WVALID , WDATA is generated by MASTER and WREADY is generated by SLAVE.
I aslo have a AXI protocol checker which now throws the error "WLAST not generated for the last write data beat" IS this an issue in the RTL or this could be waived as this is happening during timeout ?