Hi,
I am verifying a low complexity RTL design having AX Iinterface. I am working on this AXI master connected with AXI VIP slave interface. I see that in a few scenarios, when AXI master timesout, the WLAST signal is not generated at the master interface eventhough WVALID , WDATA is generated by MASTER and WREADY is generated by SLAVE.
I aslo have a AXI protocol checker which now throws the error "WLAST not generated for the last write data beat" IS this an issue in the RTL or this could be waived as this is happening during timeout ?
From what you are describing, the lack of correct WLAST assertion could be indicating where the master is broken, perhaps leading to the timeout.
This isn't something you should waive as the AXI master is still violating the AXI protocol. What if this is an error in the AXI master that sometimes happens when the master doesn't timeout (it just doesn't bother driving WLAST for the final data transfer) ?
I would suggest you work out why WLAST was not asserted at these times, fix that protocol violation, and then you might see the timeout not happen, or if it still happens at least you won't get any protocol violations reported.
Colin