ARMv8 Exception level on Startup

The Cortex-A57 supports all four Exceptions levels (EL0/1/2/3), and at reset you will be in EL3. The initial Execution state (AArch32/AArch64) is controlled by a reset signal.

To "not support" EL2/3 in your software:

Your boot code would need to route the asynchronous exceptions (IRQ/FIQ/SError) to EL1, using SCR_EL3 and HCR_EL2. If you wanted to prevent re-entry to EL2/3, you'd also need to disable use of the SMC and HVC instructions. This is also controlled via SCR_EL3 and HCR_EL2.

You'd also have do a bunch of standard initialization before entering EL1 for the first time. For example, initializing SCTLR_EL1 to a known/safe value and setting a known VMID (assuming Non-secure state).

Once you'd done the initialization, execute ERET to drop to EL1. You'll need to have set up ESR_ELx/ELR_ELx and the RW bits before this.

If you have access to DS-5, it includes a number of examples that drop from EL3 to EL1 after boot. They'd be a good starting point to see what's necessary.

Can I ask why you want to take this approach?

It's typical to have different software running at different ELs. For example, SoC/board specific firmware at EL3 and an OS at EL1. The EL1 software doesn't "support" EL3 exactly, but EL3 is being used in the system.