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Vector Table for ARMv8 (cortex A57)

Ajeesh

Hi,

 

How do i configure vector table for cortex A-57?

From the documents - "The vector table has 16 entries, with each entry being 128 bytes (32 instructions) in size. The table effectively consists of 4 sets of 4 entries"

Also " Virtual address of each table base is set by the Vector Based Address Registers VBAR_EL3, VBAR_EL2 and VBAR_EL1.".

So, do i need different vector table for each exception level EL0, EL1, EL2 and EL3? Am i to set the same vector base address for all the above base address registers?

Or Is it like, each set of 4 entries in the vector table belong to a particular exception level? 

Please help, I am really confused now.

 

Regards,

Ajeesh

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  • +1
    Hi Ajeesh,

    There are 3 vector tables, one for EL1, one for El2 and one for EL3. (That what you set in VBAR_ELx)

    Each vector table has 4 sets of entries, ie 4x IRQ handlers, 4xFIQ handlers etc. These are chosen based on the state the processor was in when the exception happened.

    Eg If you are in AArch32 EL0 and an IRQ comes in the IRQ handler at VBAR_EL1+0x680 will be used. If you are in AArch64 EL0 when th eIRQ come in the handler @VBAR_EL1+0x480 will be used. (All assuming IRQs target EL1.)

    So you end up with potentially 12 IRQ handlers, 4 per table x 3 tables.

    P
Reply
  • +1
    Hi Ajeesh,

    There are 3 vector tables, one for EL1, one for El2 and one for EL3. (That what you set in VBAR_ELx)

    Each vector table has 4 sets of entries, ie 4x IRQ handlers, 4xFIQ handlers etc. These are chosen based on the state the processor was in when the exception happened.

    Eg If you are in AArch32 EL0 and an IRQ comes in the IRQ handler at VBAR_EL1+0x680 will be used. If you are in AArch64 EL0 when th eIRQ come in the handler @VBAR_EL1+0x480 will be used. (All assuming IRQs target EL1.)

    So you end up with potentially 12 IRQ handlers, 4 per table x 3 tables.

    P
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