In the the arm gic arch specification (version 2) section 3.9.2, it has been given that for any implementation of GICv2 (with or without Security Extn)
we can configure the GIC to generate FIQ for group 0 interrupts by enabling FIQEn bit in GICC_CTLR. But it seems like that bit is reserved for the non secure copy of GICC_CTLR.
Even if I set that bit, that is not getting affected. can you please tell in this case how to configure the GIC to generate FIQ.
When the Security extensions are implemented, Group 0 interrupts are Secure. Because of this only Secure accesses can be used to configure Group 0 interrupts. This includes the Group 0 Enable and FIQEn in GICC_CTLR.
So so you need to write the Secure copy of GICC_CTLR, which you can only do from Secure state on the processor.
Hi Martin,
Thanks for the reply, please correct me if i'm missing something here.. If the processor does'not implement ,or is not using the security extensions can't we generate an FIQ from GIC ?
I'm asking this as the 3.9.2 section of this doc http://www.cl.cam.ac.uk/research/srg/han/ACS-P35/zynq/arm_gic_architecture_specification.pdf says that we can generate an FIQ