Hi, experts
I'm the new one porting armv8 linux. I have some problem about gic400 access.
In the porting linux progress,CPU will switch to EL1NS.
In gic_dist_init() function, I read the the GICD_ISENABLERn\GICD_ICENABLERn\GICD_ITARGETSRn\GICD_IPRIORITYRn registers and get 'zero' value.
Linux kernel warns the message "GIC CPU mask not found - kernel will fail to boot."
Then I can' receive any IRQ exception and I guess it's caused GIC wrong setting.
The above registers can't access by non-secure access,right?
How can I read/write correctly the gic register?
If the interrupt IDs are configured as Secure, then the corresponding fields will be RAZ/WI (Read As Zero/Writes Ignored) to Non-secure accesses. It's up to the firmware in Secure state to do some initial configuration of the GIC, including setting which interrupt IDs are Secure/Non-secure.
However, if you are just reading the registers it's entirely possible that they are just all 0s. Did you try writing them?
It's up to the firmware in Secure state to do some initial configuration of the GIC, including setting which interrupt IDs are Secure/Non-secure.
^^^^^^^^^
Do you mean the bootloader?I use the u-boot , and I need to check the configuration of interrupt ID.
Yes , I tried to writing the register. It seems doesn't work.
Since I can't not read the real value, I'm not sure the register is wrotten indeed.
Hi Martin,
I try to configure the interrupt ID as non-secure and I can read/write the registers.
Then I set the GICD_CTLR to be 0x3.(Enable the group 0/1). The value I read is '0x3'.
After cpu change to EL1NS, the value I read is '0x1'.
I tried to write '0x3',but BIT1 seems can't been write to '1'.
Many of the GIC registers behave differently depending on whether the read/write is a Secure or Non-secure access. This allows, for example, the GIC to prevent Non-secure accesses seeing or modifying the settings for Secure interrupts.
GICD_CTLR is a good example of this.
For Secure accesses: bit[0]=EnableGrp0, bit[1]=EnableGrp1
For Non-secure accesses: bit[0]=EnableGrp1, bit[1]=<unused>
In other words, a Secure access can access the enables for both Secure and Non-secure interrupts. A Non-secure access can only access the Non-secure (Group 1) enable. So what you are describing is consistent with doing a Non-secure write.
What I meant by "firmware" is the software that runs after a reset. A common sequence would look something like this:
<reset> --> boot ROM code --> firmware code from flash --> OS loaded (e.g. UEFI/U-boot) --> OS
The first two parts (boot ROM and firmware) would typically run in Secure state. And part of what they did would be to configure which interrupt sources are Secure/Non-secure. You could take a look at the ARM Trusted Firmware project in GitHub for a more concrete example.
I think the GIC setting is OK now.
Thanks your help and the information about ARM Trusted Firmware.