I don't understand the meaning of busy state behavior from ARM IHI0033B spec.
I draw the waveform to ask busy state behavior. The following is my questions.
Q1. For Read response. If the master enters busy state, which time phase does
master get correct data from the slave. data_a1_x or data_a1_y or data_a1_z or data_a1_q ?
PS: data_a1_x ≠ data_a1_y ≠ data_a1_z ≠ data_a1_q
Please see fig1
Q2: For write tansaction, if the master enters busy state which time phase doesslave can get correct data from master. data_a1_x or data_a1_y or data_a1_z or data_a1_q ?PS: data_a1_x ≠ data_a1_y ≠ data_a1_z ≠ data_a1_
Please see fig2.
Only the final diagram is the correct one to show the relationship between the AHB address and data phases of a transfer. The protocol is pipelined, with the data phase following immediately after the address phase.
If a master is not able to commit to the next address phase transfer in a burst it can issue a BUSY transfer (or an IDLE if there is no burst ongoing), and if a slave performing a NONSEQ or SEQ transfer data phase cannot complete that transfer in one cycle it can hold HREADY low for a number of cycles to add wait states.
Once a NONSEQ or SEQ transfer has entered the data phase, the master must be able to accept the read data returned by the slave, or it must be able to drive the correct write data. The master cannot stall a data phase transfer completion.
Sorry for these disjointed statements, but I'm not now too sure what you are asking.