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How was your experience today?

Does the Cortex M0+  Single-Cycle IO Bus have an address bus to decode multiple IO sets for read and write?

Alan Carr

I have an interest in the M0+ single-cycle IO Bus interface.

It seems that while the TRM describes a 32-bit bus, and a memory map it isn't clear if there is also an address bus to go along with this.

When instantiating do we have an IO address bus, and IO read/write signal as well? If so, how larger is the provided address bus for decode?

Thanks!

-Alan

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    Yes there's an address range, if you look at some of the implementations the single-cycle IO is typically used to for a GPIO interface which uses a range of a few kilobytes so the various facilities can be exploited easily. Note you can't do DMA to it directly so if for instance you want a timer to send pulses to it you'd need a separate way of doing that.

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    Yes there's an address range, if you look at some of the implementations the single-cycle IO is typically used to for a GPIO interface which uses a range of a few kilobytes so the various facilities can be exploited easily. Note you can't do DMA to it directly so if for instance you want a timer to send pulses to it you'd need a separate way of doing that.

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