I have several questions about barrier operarions.
1. how to operate barrier instructions ISB, DMB, DSB in ACE?
a) when ISB is executed, what are the signal values about barrier transaction (AxBAR, AxSNOOP , AxDOMAIN)?
b) when DMB is executed, what are the signal values about barrier transaction (AxBAR, AxSNOOP , AxDOMAIN)?
c) when DSB is executed, what are the signal values about barrier transaction (AxBAR, AxSNOOP , AxDOMAIN)?
are there any differences ?
2. as you know, there are not AxBAR in AMBA3, then how to make barrier transactions in AMBA3?
3. what is the difference barrier instructions above and MCR instruction ?
ex) MCR p15, 0, r2, c7, c10, 4
zyto said: a) when ISB is executed, what are the signal values about barrier transaction (AxBAR, AxSNOOP , AxDOMAIN)?
An ISB isn't a memory barrier and does not guarantee ordering- it's purpose is to flush the pipeline such that all instructions after the ISB are fetched from cache or memory. Therefore, an ISB wouldn't be broad on the bus.
zyto said: b) when DMB is executed, what are the signal values about barrier transaction (AxBAR, AxSNOOP , AxDOMAIN)?
A DMB would normally translate to an ACE memory barrier., where AxBAR = 01.
zyto said: c) when DSB is executed, what are the signal values about barrier transaction (AxBAR, AxSNOOP , AxDOMAIN)?
A DSB would normally translate to an ACE synchronisation barrier with AxBAR = 10.
Both barrier types will have AxSNOOP = 0000 and AxDOMAIN = any, as it depends on the shareability of the barrier instruction. For example, a DSB SY would translate to AxDOMAIN = 11.
zyto said:2. as you know, there are not AxBAR in AMBA3, then how to make barrier transactions in AMBA3?
There are no barriers in AMBA3. A system would need to ensure that transactions are observable to any master that needs to observe them when the transactions response is given.
zyto said:3. what is the difference barrier instructions above and MCR instruction ?
There is no difference, except that the MCR instructions are deprecated in ARMv8