AXI Protocol -  Strobe Signal Value

What if the size and len is 4 each and the data bus width is 256 bit ?? Kindly let me know the bits in strobe in this case. Basically I want to ask whether the strobe width depends on data width of the master or axsize? 

What if the size and len is 4 each and the data bus width is 256 bit ?? Kindly let me know the bits in strobe in this case. Basically I want to ask whether the strobe width depends on data width of the master or axsize? 

Yes, the WSTRB width directly relates to the data width.  WSTRB Width = Data Bus Width (bits) / 8

The value of the WSTRBs also depend on the signalled AWSIZE.  From A3.4.3 of the Spec - "A master must ensure that the write strobes are HIGH only for byte lanes that contain valid data."  This means that if the AWSIZE indicates that access is narrower than the data bus width, then the strobes must not indicate more bytes are being transferred than AWSIZE indicates.

So with an example.  If we have a 64 bit bus, and AWSIZE = 0x001 (2 bytes).

This means that the WSTRB width = 8.  If AWADDR[2:0] = 0x0, then the only legal WSTRB values are: 0x00, 0x01, 0x02 and 0x03, as only the bottom two bytes can be valid.

Note AWADDR matters due to narrow transfers, as described in Section A3.4.3.