Hi,
We are using Cortex-R5F. Through the AXI slave interface, we are accessing the data cache data RAM, tag RAM and dirty RAM. We would like to know how we can associate the bits found in the data RAM with the bits found in the tag RAM. For example, assuming a 4 ways cache, is the following mapping correct?:
- Offset 0 in tag RAM <- maps to -> Data Cache set 0 way 0
- Offset 4 in tag RAM <- maps to -> Data Cache set 0 way 1
- Offset 8 in tag RAM <- maps to -> Data Cache set 0 way 2
- Offset 12 in tag RAM <- maps to -> Data Cache set 0 way 3
- Offset 16 in tag RAM <- maps to -> Data Cache set 1 way 0
...
I couldn't find the answer to that question in Cortex-R5 TRM.
Thanks,
Etienne