confusing about procedure of ISR in book "ARM system developer guide"

Hi, there.

I'm new to arm family, and please bear with me of asking fundamental questions.

In book "arm system developers guide-designing and optimizing system software"

9.1.1 ARM Processor Exceptions and Modes, page 318

When an exception causes a mode change, the core automatically

1. saves the cpsr to the spsr of the exception mode

2. saves the pc to the lr of the exception mode

3. sets the cpsr to the exception mode

4. sets pc to the address of the exception handler

9.3.1 Nonnested Interrupt Handler, page 333

This section introduces various stages that occur when an interrupt is raised in a system that has implemented a simple nonnested interrupt handler with image accompanied.simple nonnested interrupt handler

1. Disable interrupt/s—When the IRQ exception is raised, the ARM processor will disable
further IRQ exceptions from occurring. The processor mode is set to the appropri-
ate interrupt request mode, and the previous cpsr is copied into the newly available
spsr_{interrupt request mode}. The processor will then set the pc to point to the correct
entry in the vector table and execute the instruction. This instruction will alter the pc to
point to the specific interrupt handler.

2. Save context—On entry the handler code saves a subset of the current processor mode
nonbanked registers.

3. Interrupt handler—The handler then identifies the external interrupt source and
executes the appropriate interrupt service routine (ISR).

4. Interrupt service routine—The ISR services the external interrupt source and resets the
interrupt.

5. Restore context—The ISR returns back to the interrupt handler, which restores the
context.

6. Enable interrupts—Finally, to return from the interrupt handler, the spsr_{interrupt
request mode} is restored back into the cpsr. The pc is then set to the next instruction
after the interrupt was raised.

I cannot link these two concept together, because I think these two is a contradiction. Here is my reasoning:

As per 9.3.1, the first action "Disable interrupt" is divided into three procedures, which are:

1. The processor mode is set to the appropriate interrupt request mode(counterpart to 3 in which section 9.1.1 says)

2. The previous cpsr is copied into the newly available spsr_{interrupt request mode}(counterpart to 1)

I think these two actions happen simultaneously?

3. The processor will then set the pc to point to the correct entry in the vector table and execute the instruction(counterpart to 4)

Wait, Where is the action 2 "saves the pc to the lr of the exception mode"?

The only way to put previous pc value into lr_interrupt is to take pc in spsr.

To conclude, the "real steps" explained in 9.1.1 are:

1. Sets the cpsr to the exception mode

2. Saves the cpsr to the spsr of the exception mode

3. Saves the pc in spsr of the exception mode to the lr of the exception mode

4. Sets pc to the address of the exception handler

Is my conclusion correct? Thank you.