The sequence of operations in the current scenario is as follows:1. Master issues an exclusive read2. Master receives EXOKAY response for this exclusive read3. Master issues an exclusive write with same id and control parameters4. Master has not yet received the response for above exclusive write.Now, is the master allowed to issue another exclusive read with same ARID? Or does the master have to wait for the write response to issue exclusive read with same ID?
Also, from the slave’s perspective, if it receives the second exclusive read before issuing write response for the exclusive write, how should the slave treat it?1. Should it accept the second read request and overwrite the exclusive monitors? In this case, whenever the slave issues response for the above write, it will issue OKAY response.2. Should the slave not accept the second read request and issue OKAY response for this read and continue with issuing EXOKAY response for the write (provided the memory is not written by any other access)?
Vanhealsing In a way it is about these instructions.
But I am more concerned about the transfers on AXI bus resulting from these instructions.
The step -> "4. Master has not yet received the response for above exclusive write", is the case when data abort exception is generated, because of failure of STREX instruction.
STREX instruction returns a result of operation to destination register Rd, which you can check and then again repeat LDREX
See more information about exclusive accesses in ARM Architecture Reference Manuals.