As we all know, ICC_SGI1R_EL1 is used to produce another core's interrupt.
I am a software engineer.
My question is what kind of memory barrier should be followed by writes ICC_SGI1R_EL1?
This question related to the implementation of the instruction "MSR ICC_SGI1R_EL1, x".
If the instruction actually write the memory mapped register, should we use data memory barrier?
I doubt there is a memory barrier needed for this register. Memory barrier is needed if the delayed effect of writing might cause problems.For example if you use shared memory to store information, do the SGI and another core reads this memory. Then you might need a "DMB" _before_ SGI. But not after. As the current core does not rely on it.Different example is changing MMU config, then you need the DMB _after_ changing it, to be sure the next insn sees the effect.
Yes, Thanks!
But I see linux add a ISB after it.
https://code.woboq.org/linux/linux/drivers/irqchip/irq-gic-v3.c.html#763
There is a comments /* Force the above writes to ICC_SGI1R_EL1 to be executed */.
Does this write need to be forced?
There is an interesting chapter in the ARMv8-A manual: D7.1.2 .My understanding is, the Linux code is "defensive" here. Means, they want to make sure, that the SGI has been handled before any other action takes place which might rely on it. Since the code might also send an IPI to the local core this might be the reason for this.I use SGI heavily for Core to Core message passing on ARMv7 and ARMv8 but did not notice any problem.
In <ARM® Generic Interrupt Controller Architecture Specification>
There is a NOTICE:
An ISB or other context synchronization operation must precede the DSB to ensure visibility of System register writes.
According to this, we should add both ISB and DSB to make other core see it.
The GIC 3.0 manual is the only one with this hint. Maybe one reason you did notice this dramatic difference in the latency between 2.0 and 3.0?