Consider a hypervisor injecting a hardware interrupt in a virtual machine, by setting the HW bit in a List Register (LR).According to the GICv{2,3,4} specification, after the virtual machine has taken the interrupt, the value of the State field in the LR is unreliable. Software can never know for certain whether the virtual interrupt is still pending, or active, or has been deactivated. All it can do is poll the physical distributor until the physical interrupt has been deactivated, at which point it knows that the virtual interrupt has been deactivated as well.However, the GIC provides GICH_ELRSR/ICH_ELRSR_EL2 to determine which List Registers contain valid interrupts; in particular, for a hardware interrupt, the corresponding bit is set if and only if the LR's State field is 0. My problem is that, according to the previous paragraph, the value of this State field is unpredictable.So, which one of the following statements is true?1. Some time after the virtual interrupt has been deactivated (possibly immediately), the State field in the LR will be cleared, and the hypervisor will know it has happened when it sees the corresponding bit set in GICH_ELRSR/ICH_ELRSR_EL2.2. The value of the State field in the LR can never be relied on, and the bit in GICH_ELRSR/ICH_ELRSR_EL2 corresponding to the hardware interrupt is meaningless in practice. The hypervisor must poll the bit corresponding to the physical interrupt in GICD_ICACTIVER or GICD_ISACTIVER instead.If statement 2 is true, then why does the specification for GICH_ELRSR/ICH_ELRSR_EL2 mention hardware interrupts in the first place? And what about the No Pending and Underfow maintenance interrupts? Could the unpredictability of LR State values for hardware interrupts prevent those maintenance interrupts from being asserted?