In GICv2, per-core interrupts (SGIs and PPIs) are configured through banked registers in the distributor, which means that a core cannot access the configuration of the SGIs and PPIs of the other cores.
By contrast, GICv3 moves this configuration to redistributors, which are apparently mapped at pairwise distinct addresses, and it seems that every distributor can be accessed by every core (although the spec is unclear on this point). For instance, on some operating systems, a core will scan regions of redistributors in memory, using GICR_TYPER.Affinity_Value to match them to cores, and GICR_TYPER.Last to discover where a region ends.
Does it mean that an implementation is required to allow every core to configure the SGIs and PPIs of every other core?